/********************************************************************
* @Copyright: Metanergy Technology R&D Co., Ltd
* @Filename: myg0025_adc.h
* @brief  : This file contains all the functions prototypes for the ADC firmware
*          library
* @Author : AE Team
********************************************************************/

#ifndef __MYG0025_adc__
#define __MYG0025_adc__

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "myg0025.h"

/** @addtogroup ADC
  * @{
  */

/** @defgroup ADC_Exported_Types ADC_Exported_Types
  * @{
  */
/* Exported types ------------------------------------------------------------*/

/** @defgroup ADC_common_macro ADC_common_macro
  * @{
  */
#define     IS_ADC_ALL_PERIPH(STATE)            (((STATE) == ADC))
#define     IS_TIME(TIME)                       (((TIME) <= 0xFFFFFFFF))
#define     CALIBRATION_TIMEOUT                 5000
#define     MAX_ELEMENT_NUM                     8
#define     TEMP85_CAL_ADDR                     ((uint16_t*) ((uint32_t) 0x1ffff60E))
#define     TEMP25_CAL_ADDR                     ((uint16_t*) ((uint32_t) 0x1ffff60c))
#define     VREFINT_CAL_ADDR                    ((uint16_t*) ((uint32_t) 0x1ffff614))
#define     TEMPS_CAL_ADDR                      ((uint32_t)0x1ffff612)
#define     CALIBRATION_TIME                    1000000
#define     SOFT_CALIBRATION_TIME               1000
/**
  * @}
  */

/**
  * @brief  ADC Init structure definition
  */

typedef struct
{
    uint32_t ADC_ClockDiv;                    /*!< Selects the Adc clock division
                                                 This parameter can be a value of @ref ADC_clockdiv */
    uint32_t ADC_TrigDiv;                                           /*!< Selects the Adc triger division
                                                 This parameter can be a value of @ref ADC_trigdiv */
    uint32_t ADC_Sample_Hold;                                   /*!< Selects the Adc sample hold time
                                                 This parameter can be a value of @ref ADC_sample_hold */
    uint32_t ADC_Chl_Hold;                                    /*!< Selects the Adc channel hold time
                                                 This parameter can be a value of @ref ADC_chl_hold */

    uint32_t ADC_SH_Sample_Cycle;             /*!< Selects the Adc SHx sample cycle
                                                 This parameter can be a value of @ref ADC_sh_sample_cycle */

    uint32_t ADC_EOC_SOC_DIS;                 /*!< Selects the Adc sample cycle
                                                 This parameter can be a value of @ref ADC_eoc_soc_dis */
    uint32_t ADC_Power_Mode;                  /*!< Selects the Adc power mode
                                                 This parameter can be a value of @ref ADC_powermode */
} ADC_InitTypeDef;


/**
  * @brief  ADC Queue Init structure definition
  */

typedef struct
{
    uint32_t ADC_Queue;                       /*!< Selects the Adc queue
                                                 This parameter can be a value of @ref ADC_queue */

    FunctionalState ADC_Queue_CirculationMode;   /*!< Specifies whether the conversion is performed in
                                                 Continuous or Single mode.
                                                 This parameter can be set to ENABLE or DISABLE. */

    FunctionalState ADC_Queue_StepMode;         /*!< Specifies whether the conversion is performed in step mode.
                                                 This parameter can be set to ENABLE or DISABLE.
                                                                                                 ADC_Queue_CirculationMode and ADC_StepMode Can't be ENABLE at the same time */

    FunctionalState ADC_Queue_SWTrig;               /*!< Specifies whether support software trigger
                                                 This parameter can be set to ENABLE or DISABLE. */

    uint32_t ADC_TestQueue_ExternalTrigConvEdge;  /*!< Selects the external trigger Edge and enables the
                                                 trigger of a regular group.
                                                                                                 when the ADC_Queue is QUEUE_TEST This parameter can be a value of @ref ADC_test_ext_trig
                                                                                                 others is @ref ADC_ext_trig_edge
                                                                                                 note: when disable the txternal trig, this parameter is EXT_TRIG_DIS or TEST_EXT_TRIG_DIS*/

    uint32_t ADC_TestQueue_ExternalTrigConv;      /*!< Defines the external trigger used to start the analog
                                                 to digital channel conversion of queue.
                                                                                                 when the ADC_Queue is QUEUE_TEST This parameter can be a value of @ref ADC_test_external_trigger_sources
                                                                                                 others is @ref ADC_external_trigger_sources*/

    uint32_t ADC_Queue_ExternalTrigConvEdge;  /*!< Selects the external trigger Edge and enables the
                                                 trigger of a regular group.
                                                                                                 when the ADC_Queue is QUEUE_TEST This parameter can be a value of @ref ADC_test_ext_trig
                                                                                                 others is @ref ADC_ext_trig_edge
                                                                                                 note: when disable the txternal trig, this parameter is EXT_TRIG_DIS or TEST_EXT_TRIG_DIS*/

    uint32_t ADC_Queue_ExternalTrigConv;      /*!< Defines the external trigger used to start the analog
                                                 to digital channel conversion of queue.
                                                                                                 when the ADC_Queue is QUEUE_TEST This parameter can be a value of @ref ADC_test_external_trigger_sources
                                                                                                 others is @ref ADC_external_trigger_sources*/

    FunctionalState ADC_Queue_ExternalGpioFilter; /*!< Specifies whether support external gpio trigger filter function
                                                 This parameter can be set to ENABLE or DISABLE. */

    uint32_t ADC_Queue_Mode;                  /*!< Selects the queue mode
                                                 when the ADC_Queue is QUEUE_TEST This parameter can be a value of @ref ADC_test_que_mode
                                                                                                 others is @ref ADC_queue_mode*/

    uint32_t ADC_Queue_Priority;              /*!< Selects the queue priority
                                                 This parameter can be a value of @ref ADC_queue_priority */

    uint32_t ADC_Queue_Element;               /*!< Selects the queue element
                                                                                                 This parameter can be a value of @ref ADC_queue_element */

    uint32_t ADC_Queue_Channel[MAX_ELEMENT_NUM]; /*!< Selects the queue channel
                                                 This parameter can be a value of @ref ADC_channel
                                                                                                 ADC_Queue_Channel[0] corresponding to QUEUE_1ST_CHL
                                                                                                 ADC_Queue_Channel[1] corresponding to QUEUE_2ST_CHL
                                                                                                 ADC_Queue_Channel[2] corresponding to QUEUE_3ST_CHL
                                                                                                 ADC_Queue_Channel[3] corresponding to QUEUE_4ST_CHL
                                                                                                 ADC_Queue_Channel[4] corresponding to QUEUE_5ST_CHL
                                                                                                 ADC_Queue_Channel[5] corresponding to QUEUE_6ST_CHL
                                                                                                 ADC_Queue_Channel[6] corresponding to QUEUE_7ST_CHL
                                                                                                 ADC_Queue_Channel[7] corresponding to QUEUE_8ST_CHL*/
    uint32_t ADC_Test_Queue_Channel;                    /*!< Selects the test queue channel
                                                 This parameter can be a value of @ref ADC_test_channel*/

    uint32_t ADC_Queue_Sample_Cycle;          /*!< Selects the Adc sample cycle, this parameter only valid when ADC_Queue_Mode is QUEUE_MODE_SH_BYPASS or QUEUE_MODE_SH_BKP
                                                 This parameter can be a value of @ref ADC_sampletime */
    FunctionalState ADC_Test_Queue_BK;              /*!< Specifies whether enable the test queue bk mode
                                                 This parameter can be set to ENABLE or DISABLE. */
    FunctionalState ADC_Queue_Replace;              /*!< Specifies whether enable the channel repalce function
                                                 This parameter can be set to ENABLE or DISABLE. */
    uint32_t ADC_Queue_Replace_Channel[MAX_ELEMENT_NUM]; /*!< Selects the queue repalce channel
                                                 This parameter can be a value of @ref ADC_channel
                                                                                                 ADC_Queue_Replace_Channel[0] corresponding to REPLACE_1ST_CHL
                                                                                                 ADC_Queue_Replace_Channel[1] corresponding to REPLACE_2ST_CHL
                                                                                                 ADC_Queue_Replace_Channel[2] corresponding to REPLACE_3ST_CHL
                                                                                                 ADC_Queue_Replace_Channel[3] corresponding to REPLACE_4ST_CHL
                                                                                                 ADC_Queue_Replace_Channel[4] corresponding to REPLACE_5ST_CHL
                                                                                                 ADC_Queue_Replace_Channel[5] corresponding to REPLACE_6ST_CHL
                                                                                                 ADC_Queue_Replace_Channel[6] corresponding to REPLACE_7ST_CHL
                                                                                                 ADC_Queue_Replace_Channel[7] corresponding to REPLACE_8ST_CHL*/
} Queue_InitTypeDef;


/**
  * @}
  */

/** @defgroup ADC_Exported_Constants ADC_Exported_Constants
    * @brief ADC exported constants
  * @{
    @verbatim
    @endverbatim
  */
/* Exported types ------------------------------------------------------------*/

/** @defgroup ADC_sh_mode ADC_sh_mode
  * @{
  */
#define   SH_MODE_0         ADC_SYSCFGR1_S_H0_EN_Pos
#define   SH_MODE_1         ADC_SYSCFGR1_S_H1_EN_Pos
#define   IS_SH_INDEX(SH_INDEX) (((SH_INDEX) == SH_MODE_0) || ((SH_INDEX) == SH_MODE_1))
/**
  * @}
  */

/** @defgroup ADC_clockdiv ADC_clockdiv
  * @{
  */
#define   ADC_ClockDiv_1  0
#define   ADC_ClockDiv_2  1
#define   ADC_ClockDiv_4  2
#define   ADC_ClockDiv_8  3
#define   IS_ADC_CLOCKDIV(CLOCKDIV)   (((CLOCKDIV) == ADC_ClockDiv_1) || ((CLOCKDIV) == ADC_ClockDiv_2) || ((CLOCKDIV) == ADC_ClockDiv_4) || ((CLOCKDIV) == ADC_ClockDiv_8) )
/**
  * @}
  */

/** @defgroup ADC_trigdiv ADC_trigdiv
  * @{
  */
#define   ADC_TrigDiv_1         0
#define   ADC_TrigDiv_2         1
#define   ADC_TrigDiv_4         2
#define   ADC_TrigDiv_8         3
#define   ADC_TrigDiv_16        4
#define   ADC_TrigDiv_32        5
#define   ADC_TrigDiv_64        6
#define   ADC_TrigDiv_128       7
#define   IS_ADC_TRIGDIV(CLOCKTRIG)   (((CLOCKTRIG) == ADC_TrigDiv_1) || ((CLOCKTRIG) == ADC_TrigDiv_16) || \
                                        ((CLOCKTRIG) == ADC_TrigDiv_2) || ((CLOCKTRIG) == ADC_TrigDiv_32) || \
                                        ((CLOCKTRIG) == ADC_TrigDiv_4) || ((CLOCKTRIG) == ADC_TrigDiv_64) || \
                                        ((CLOCKTRIG) == ADC_TrigDiv_8) || ((CLOCKTRIG) == ADC_TrigDiv_128))
/**
  * @}
  */

/** @defgroup ADC_dma_channel ADC_dma_channel
  * @{
  */
#define   DMA_CHANNEL_QUE0          ADC_SYSCFGR1_DMA_QUE0_EN_Pos
#define   DMA_CHANNEL_QUE1          ADC_SYSCFGR1_DMA_QUE1_EN_Pos
#define   DMA_CHANNEL_QUE2          ADC_SYSCFGR1_DMA_QUE2_EN_Pos
#define   DMA_CHANNEL_QUE3          ADC_SYSCFGR1_DMA_QUE3_EN_Pos
#define   DMA_CHANNEL_QUECOMM   ADC_SYSCFGR1_DMA_COMM_EN_Pos
#define   IS_ADC_DMA_CHANNEL(DMA_CHANNEL)   (DMA_CHANNEL != (uint32_t)0)
/**
  * @}
  */


/** @defgroup ADC_powermode ADC_powermode
  * @{
  */
#define   ADC_LOWER_POWER_MODE  0
#define   ADC_HIGN_POWER_MODE       1
#define   IS_POWER_MODE_STATE(PWR_MODE) (((PWR_MODE) == ADC_LOWER_POWER_MODE) || ((PWR_MODE) == ADC_HIGN_POWER_MODE))
/**
  * @}
  */



/** @defgroup ADC_it ADC_it
  * @{
  */
#define   ADC_IT_ADRDY                  ADC_ISR_ADC_RDY
#define   ADC_IT_EOC_COMM               ADC_ISR_EOC_COMM
#define   ADC_IT_EOC_QUE0               ADC_ISR_EOC_QUE0
#define   ADC_IT_EOC_QUE1               ADC_ISR_EOC_QUE1
#define   ADC_IT_EOC_QUE2               ADC_ISR_EOC_QUE2
#define   ADC_IT_EOC_QUE3               ADC_ISR_EOC_QUE3
#define   ADC_IT_EOC_TEST               ADC_ISR_EOC_TEST
#define   ADC_IT_OVR                    ADC_ISR_OVR
#define   ADC_IT_COMP_DALM              ADC_ISR_COMP_DALM
#define   ADC_IT_COMP_UALM              ADC_ISR_COMP_UALM
#define   ADC_IT_OVR0                   ADC_ISR_OVR0
#define   ADC_IT_OVR1                   ADC_ISR_OVR1
#define   ADC_IT_OVR2                   ADC_ISR_OVR2
#define   ADC_IT_OVR3                   ADC_ISR_OVR3
#define   ADC_IT_OVR4                   ADC_ISR_OVR4
#define   ADC_IT_OVR5                   ADC_ISR_OVR5
#define   ADC_IT_OVR6                   ADC_ISR_OVR6
#define   ADC_IT_OVR7                   ADC_ISR_OVR7
#define   ADC_IT_OVR8                   ADC_ISR_OVR8
#define   ADC_IT_OVR9                   ADC_ISR_OVR9
#define   ADC_IT_OVR10                  ADC_ISR_OVR10
#define   ADC_IT_OVR11                  ADC_ISR_OVR11
#define   ADC_IT_OVR12                  ADC_ISR_OVR12
#define   ADC_IT_OVR13                  ADC_ISR_OVR13
#define   ADC_IT_OVR14                  ADC_ISR_OVR14
#define   ADC_IT_OVR15                  ADC_ISR_OVR15
#define   IS_ADC_IT(IT_FLAG) ((IT_FLAG) != (uint32_t)0)
/**
  * @}
  */

/** @defgroup ADC_queue ADC_queue
  * @{
  */
#define   QUEUE_0                                   0
#define   QUEUE_1                                   1
#define   QUEUE_2                                   2
#define   QUEUE_3                                   3
#define   QUEUE_TEST                                4
#define   IS_QUE_INDEX(QUE_INDEX) (((QUE_INDEX) == QUEUE_0) || ((QUE_INDEX) == QUEUE_1) || \
                  ((QUE_INDEX) == QUEUE_2) || ((QUE_INDEX) == QUEUE_3) || ((QUE_INDEX) == QUEUE_TEST))
/**
  * @}
  */


/** @defgroup ADC_queue_element ADC_queue_element
  * @{
  */
#define   ELEMENT_0                             ADC_SQUE0_CFG1_E0
#define   ELEMENT_1                             ADC_SQUE0_CFG1_E1
#define   ELEMENT_2                             ADC_SQUE0_CFG1_E2
#define   ELEMENT_3                             ADC_SQUE0_CFG1_E3
#define   ELEMENT_4                             ADC_SQUE0_CFG1_E4
#define   ELEMENT_5                             ADC_SQUE0_CFG1_E5
#define   ELEMENT_6                             ADC_SQUE0_CFG1_E6
#define   ELEMENT_7                             ADC_SQUE0_CFG1_E7
#define   ELEMENT_8                             ADC_SQUE0_CFG1_E8
#define   ELEMENT_9                             ADC_SQUE0_CFG1_E9
#define   ELEMENT_10                            ADC_SQUE0_CFG1_E10
#define   ELEMENT_11                            ADC_SQUE0_CFG1_E11
#define   ELEMENT_12                            ADC_SQUE0_CFG1_E12
#define   ELEMENT_13                            ADC_SQUE0_CFG1_E13
#define   ELEMENT_14                            ADC_SQUE0_CFG1_E14
#define   ELEMENT_15                            ADC_SQUE0_CFG1_E15
#define   ELEMENT_ALL                           0xFFFF0000
#define   IS_ADC_ELEMENT(ELEMENT) (ELEMENT <= ELEMENT_ALL)



/**
  * @}
  */

/** @defgroup ADC_ext_trig_edge ADC_ext_trig_edge
  * @{
  */
#define   EXT_TRIG_DIS                       0
#define   EXT_TRIG_RISING                    1
#define   EXT_TRIG_FALLING                   2
#define   EXT_TRIG_RISING_FALLING            3
#define   IS_EXT_TRIG(EXT_TRIG) (((EXT_TRIG) == EXT_TRIG_DIS) || ((EXT_TRIG) == EXT_TRIG_RISING) || \
                                 ((EXT_TRIG) == EXT_TRIG_FALLING) || ((EXT_TRIG) == EXT_TRIG_RISING_FALLING))
/**
  * @}
  */

/** @defgroup ADC_trig_dly ADC_trig_dly
  * @{
  */
#define   EXT_TRIG_DLY0                     (0<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   EXT_TRIG_DLY1                     (1<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   EXT_TRIG_DLY2                     (2<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   EXT_TRIG_DLY3                     (3<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   EXT_TRIG_DLY4                     (4<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   EXT_TRIG_DLY5                     (5<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   EXT_TRIG_DLY6                     (6<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   EXT_TRIG_DLY7                     (7<<ADC_SQUE0_CFG2_TRIG_DLY_CNT_Pos)
#define   IS_ADC_TRIG_DLY(EXT_TRIG_DLY) (((EXT_TRIG_DLY) == EXT_TRIG_DLY0) || ((EXT_TRIG_DLY) == EXT_TRIG_DLY1) || \
                  ((EXT_TRIG_DLY) == EXT_TRIG_DLY2) || ((EXT_TRIG_DLY) == EXT_TRIG_DLY3) || ((EXT_TRIG_DLY) == EXT_TRIG_DLY4) || \
                    ((EXT_TRIG_DLY) == EXT_TRIG_DLY5) || ((EXT_TRIG_DLY) == EXT_TRIG_DLY6) || ((EXT_TRIG_DLY) == EXT_TRIG_DLY7))
/**
  * @}
  */

/** @defgroup ADC_queue_chl ADC_queue_chl
  * @{
  */
#define   QUEUE_1ST_CHL                     0
#define   QUEUE_2ST_CHL                     1
#define   QUEUE_3ST_CHL                     2
#define   QUEUE_4ST_CHL                     3
#define   QUEUE_5ST_CHL                     4
#define   QUEUE_6ST_CHL                     5
#define   QUEUE_7ST_CHL                     6
#define   QUEUE_8ST_CHL                     7
#define   IS_ADC_QUEUE_CHL(QUEUE_CHL) (((QUEUE_CHL) == QUEUE_1ST_CHL) || ((QUEUE_CHL) == QUEUE_2ST_CHL) || \
                  ((QUEUE_CHL) == QUEUE_3ST_CHL) || ((QUEUE_CHL) == QUEUE_4ST_CHL) || ((QUEUE_CHL) == QUEUE_5ST_CHL) || \
                    ((QUEUE_CHL) == QUEUE_6ST_CHL) || ((QUEUE_CHL) == QUEUE_7ST_CHL) || ((QUEUE_CHL) == QUEUE_8ST_CHL))
/**
  * @}
  */


/** @defgroup ADC_replace_chl ADC_replace_chl
  * @{
  */
#define   REPLACE_1ST_CHL                   0
#define   REPLACE_2ST_CHL                   1
#define   REPLACE_3ST_CHL                   2
#define   REPLACE_4ST_CHL                   3
#define   REPLACE_5ST_CHL                   4
#define   REPLACE_6ST_CHL                   5
#define   REPLACE_7ST_CHL                   6
#define   REPLACE_8ST_CHL                   7
#define   IS_REPLACE_CHL(REPLACE_CHL) (((REPLACE_CHL) == REPLACE_1ST_CHL) || ((REPLACE_CHL) == REPLACE_2ST_CHL) || \
                  ((REPLACE_CHL) == REPLACE_3ST_CHL) || ((REPLACE_CHL) == REPLACE_4ST_CHL) || ((REPLACE_CHL) == REPLACE_5ST_CHL) || \
                    ((REPLACE_CHL) == REPLACE_6ST_CHL) || ((REPLACE_CHL) == REPLACE_7ST_CHL) || ((REPLACE_CHL) == REPLACE_8ST_CHL))
/**
  * @}
  */


/** @defgroup ADC_average_element ADC_average_element
  * @{
  */
#define   ELEMENT_Q0                                ADC_SQUE0_AVERAGE_D0
#define   ELEMENT_Q1                                ADC_SQUE0_AVERAGE_D1
#define   ELEMENT_Q2                                ADC_SQUE0_AVERAGE_D2
#define   ELEMENT_Q3                                ADC_SQUE0_AVERAGE_D3
#define   ELEMENT_Q4                                ADC_SQUE0_AVERAGE_D4
#define   ELEMENT_Q5                                ADC_SQUE0_AVERAGE_D5
#define   ELEMENT_Q6                                ADC_SQUE0_AVERAGE_D6
#define   ELEMENT_Q7                                ADC_SQUE0_AVERAGE_D7
#define   IS_AVERAGE_ELEMENT(AVERAGE_ELEMENT) ((AVERAGE_ELEMENT) != (uint32_t)0)
/**
  * @}
  */

/** @defgroup ADC_test_channel ADC_test_channel
  * @{
  */
#define   TEST_CHANNEL_0                                    0
#define   TEST_CHANNEL_1                                    1
#define   TEST_CHANNEL_2                                    2
#define   TEST_CHANNEL_3                                    3
#define   TEST_CHANNEL_4                                    4
#define   TEST_CHANNEL_5                                    5
#define   TEST_CHANNEL_6                                    6
#define   TEST_CHANNEL_7                                    7
#define   TEST_CHANNEL_8                                    8
#define   TEST_CHANNEL_9                                    9

#define   TEST_CHANNEL_OPAMP1                               10
#define   TEST_CHANNEL_OPAMP2                               11
#define   TEST_CHANNEL_OPAMP3                               12
#define   TEST_CHANNEL_VOLTAGE_DIV                          13

#define   TEST_BK_CHANNEL_OPAMP1                            11
#define   TEST_BK_CHANNEL_OPAMP2                            13
#define   TEST_BK_CHANNEL_OPAMP3                            14
#define   TEST_BK_CHANNEL_VOLTAGE_DIV                       15
#define   TEST_BK_CHANNEL_VREFINT                           16
#define   TEST_BK_CHANNEL_LDO                               17

#define   IS_ADC_TEST_CHANNEL(TEST_CHANNEL) (((TEST_CHANNEL) == TEST_CHANNEL_0) || ((TEST_CHANNEL) == TEST_CHANNEL_1) || \
                                             ((TEST_CHANNEL) == TEST_CHANNEL_2) || ((TEST_CHANNEL) == TEST_CHANNEL_3) || \
                                             ((TEST_CHANNEL) == TEST_CHANNEL_4) || ((TEST_CHANNEL) == TEST_CHANNEL_5) || \
                                             ((TEST_CHANNEL) == TEST_CHANNEL_6) || ((TEST_CHANNEL) == TEST_CHANNEL_7) || \
                                             ((TEST_CHANNEL) == TEST_CHANNEL_8) || ((TEST_CHANNEL) == TEST_CHANNEL_9) || \
                                             ((TEST_CHANNEL) == TEST_CHANNEL_OPAMP1) || ((TEST_CHANNEL) == TEST_CHANNEL_OPAMP2)|| \
                                             ((TEST_CHANNEL) == TEST_CHANNEL_VOLTAGE_DIV) || ((TEST_CHANNEL) == TEST_BK_CHANNEL_OPAMP1)|| \
                                             ((TEST_CHANNEL) == TEST_BK_CHANNEL_OPAMP2) || ((TEST_CHANNEL) == TEST_BK_CHANNEL_VOLTAGE_DIV)|| \
                                             ((TEST_CHANNEL) == TEST_BK_CHANNEL_VREFINT) || ((TEST_CHANNEL) == TEST_BK_CHANNEL_LDO) ||\
                                             ((TEST_CHANNEL) == TEST_CHANNEL_OPAMP3) || ((TEST_CHANNEL) == TEST_BK_CHANNEL_OPAMP3))
/**
  * @}
  */

/** @defgroup ADC_queue_mode ADC_queue_mode
  * @{
  */
#define   QUEUE_MODE_SH_DUAL                    0
#define   QUEUE_MODE_SH_SINGLE                  1
#define   QUEUE_MODE_SH_SCAN1                   3
#define   QUEUE_MODE_SH_SCAN2                   4
#define   QUEUE_MODE_SH_BKP                     5
#define   IS_QUEUE_MODE(UEUE_MODE) (((UEUE_MODE) == QUEUE_MODE_SH_DUAL) || ((UEUE_MODE) == QUEUE_MODE_SH_SINGLE) || \
                                    ((UEUE_MODE) == QUEUE_MODE_SH_BKP) || ((UEUE_MODE) == QUEUE_MODE_SH_SCAN1) || \
                                    ((UEUE_MODE) == QUEUE_MODE_SH_SCAN2))
/**
  * @}
  */

/** @defgroup ADC_channel ADC_channel
  * @{
  */
#define     ADC_Channel_0                           0
#define     ADC_Channel_1                           1
#define     ADC_Channel_2                           2
#define     ADC_Channel_3                           3
#define     ADC_Channel_4                           4
#define     ADC_Channel_5                           5
#define     ADC_Channel_6                           6
#define     ADC_Channel_7                           7
#define     ADC_Channel_8                           8
#define     ADC_Channel_9                           9
/*OPAMP1_OUT*/
#define     ADC_Channel_10                          10
/*OPAMP2_OUT*/
#define     ADC_Channel_11                          11
/*OPAMP3_OUT*/
#define     ADC_Channel_12                          12
/*VOLTAGE_DIV*/
#define     ADC_Channel_13                          13
#define   IS_CHANNEL_INDEX(CHANNEL) ((CHANNEL) <= (uint32_t)ADC_Channel_13)
/**
  * @}
  */

/** @defgroup ADC_queue_priority ADC_queue_priority
  * @{
  */
#define   PRIORITY_0                                    0
#define   PRIORITY_1                                    1
#define   PRIORITY_2                                    2
#define   PRIORITY_3                                    3
#define   IS_ADC_PRIORITY(PRIORITY) (((PRIORITY) == PRIORITY_0) || ((PRIORITY) == PRIORITY_1) || \
                                    ((PRIORITY) == PRIORITY_2) || ((PRIORITY) == PRIORITY_3))
/**
  * @}
  */

/** @defgroup ADC_eoc_soc_dis ADC_eoc_soc_dis
  * @{
  */
#define   EOC_SOC_DIS_1_5_Cycles                    ((uint32_t)0x00000000)
#define   EOC_SOC_DIS_4_5_Cycles                    ((uint32_t)0x00000001)
#define   EOC_SOC_DIS_10_5_Cycles                   ((uint32_t)0x00000002)
#define   EOC_SOC_DIS_14_5_Cycles                   ((uint32_t)0x00000003)
#define   IS_ADC_Distance(EOC_DIS) (((EOC_DIS) == EOC_SOC_DIS_1_5_Cycles) || ((EOC_DIS) == EOC_SOC_DIS_4_5_Cycles) || \
                                   ((EOC_DIS) == EOC_SOC_DIS_10_5_Cycles) || ((EOC_DIS) == EOC_SOC_DIS_14_5_Cycles))
/**
  * @}
  */

/** @defgroup ADC_chl_hold ADC_chl_hold
  * @{
  */
#define   CHL_HOLD_NO                           ((uint32_t)0x00000000)
#define   CHL_HOLD_0_5_Cycles                   ((uint32_t)0x00000001)
#define   CHL_HOLD_1_Cycles                     ((uint32_t)0x00000002)
#define   CHL_HOLD_1_5_Cycles                   ((uint32_t)0x00000003)
#define   IS_ADC_CHLHOLD(HOLD) (((HOLD) == CHL_HOLD_NO) || ((HOLD) == CHL_HOLD_0_5_Cycles) || \
                               ((HOLD) == CHL_HOLD_1_Cycles) || ((HOLD) == CHL_HOLD_1_5_Cycles))
/**
  * @}
  */


/** @defgroup ADC_sh_sample_cycle ADC_sh_sample_cycle
  * @{
    * @brief The sampling period of SH
  */
#define     ADC_SAMPLE_CYCLE1_1_Cycles  ((uint32_t)0x00000000)
#define     ADC_SAMPLE_CYCLE1_2_Cycles  ((uint32_t)0x00000001)
#define     ADC_SAMPLE_CYCLE1_3_Cycles  ((uint32_t)0x00000002)
#define     ADC_SAMPLE_CYCLE1_4_Cycles  ((uint32_t)0x00000003)
#define     ADC_SAMPLE_CYCLE1_5_Cycles  ((uint32_t)0x00000004)
#define     ADC_SAMPLE_CYCLE1_6_Cycles  ((uint32_t)0x00000005)
#define     ADC_SAMPLE_CYCLE1_7_Cycles  ((uint32_t)0x00000006)
#define     ADC_SAMPLE_CYCLE1_8_Cycles  ((uint32_t)0x00000007)
#define   IS_ADC_SAMPLE_CYCLE1(SAMPLE_CYCLE1) (((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_1_Cycles) || ((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_2_Cycles) || \
                                               ((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_3_Cycles) || ((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_4_Cycles) || \
                                               ((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_5_Cycles) || ((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_6_Cycles)|| \
                                               ((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_7_Cycles) || ((SAMPLE_CYCLE1) == ADC_SAMPLE_CYCLE1_8_Cycles))
/**
  * @}
  */

/** @defgroup ADC_sampletime ADC_sampletime
    * @brief The sampling time of the ADC, only used in BK mode.
  * @{
  */
#define     ADC_SampleTime_1_5Cycles    ((uint32_t)0x00000000)
#define     ADC_SampleTime_7_5Cycles    ((uint32_t)0x00000001)
#define     ADC_SampleTime_13_5Cycles   ((uint32_t)0x00000002)
#define     ADC_SampleTime_28_5Cycles   ((uint32_t)0x00000003)
#define     ADC_SampleTime_41_5Cycles   ((uint32_t)0x00000004)
#define     ADC_SampleTime_55_5Cycles   ((uint32_t)0x00000005)
#define     ADC_SampleTime_71_5Cycles   ((uint32_t)0x00000006)
#define     ADC_SampleTime_239_5Cycles  ((uint32_t)0x00000007)
#define   IS_ADC_SAMPLE_TIME(SAMPLE_TIME) (((SAMPLE_TIME) == ADC_SampleTime_1_5Cycles) || ((SAMPLE_TIME) == ADC_SampleTime_7_5Cycles) || \
                                            ((SAMPLE_TIME) == ADC_SampleTime_13_5Cycles) || ((SAMPLE_TIME) == ADC_SampleTime_28_5Cycles) || \
                                            ((SAMPLE_TIME) == ADC_SampleTime_41_5Cycles) || ((SAMPLE_TIME) == ADC_SampleTime_55_5Cycles)|| \
                                            ((SAMPLE_TIME) == ADC_SampleTime_71_5Cycles) || ((SAMPLE_TIME) == ADC_SampleTime_239_5Cycles))
/**
  * @}
  */


/** @defgroup ADC_external_trigger_sources ADC_external_trigger_sources
  * @{
  */
#define   EXT_TIM_MASK   (ADC_SQUE0_CFG2_TIM3_TRGO_SEL | ADC_SQUE0_CFG2_TIM2_TRGO_SEL | ADC_SQUE0_CFG2_TIM1_CC6_SEL \
                                                | ADC_SQUE0_CFG2_TIM1_CC5_SEL | ADC_SQUE0_CFG2_TIM1_CC4_SEL | ADC_SQUE0_CFG2_TIM1_TRGO_SEL)

#define   EXT_TIM1_NONE         0
#define   EXT_TIM1_TRGO         ADC_SQUE0_CFG2_TIM1_TRGO_SEL
#define   EXT_TIM1_CC4          ADC_SQUE0_CFG2_TIM1_CC4_SEL
#define   EXT_TIM1_CC5          ADC_SQUE0_CFG2_TIM1_CC5_SEL
#define   EXT_TIM1_CC6          ADC_SQUE0_CFG2_TIM1_CC6_SEL
#define   EXT_TIM2_TRGO         ADC_SQUE0_CFG2_TIM2_TRGO_SEL
#define   EXT_TIM3_TRGO         ADC_SQUE0_CFG2_TIM3_TRGO_SEL
#define   EXT_GPIO_TRGI         ADC_SQUE0_CFG2_EXT_TRIG_SEL
#define   IS_EXT_TIM(EXT_TIM) (EXT_TIM <= (EXT_TIM1_TRGO | EXT_TIM1_CC4 | EXT_TIM1_CC5 | EXT_TIM1_CC6 |\
                                           EXT_TIM2_TRGO | EXT_TIM3_TRGO | EXT_GPIO_TRGI))
/**
  * @}
  */


/** @defgroup ADC_test_external_trigger_sources ADC_test_external_trigger_sources
  * @{
  */
#define   TEST_EXT_TIM_MASK   (ADC_TEST_CHL_CFG_TIM3_TRGO_SEL | ADC_TEST_CHL_CFG_TIM2_TRGO_SEL \
                             | ADC_TEST_CHL_CFG_TIM1_CC6_SEL | ADC_TEST_CHL_CFG_TIM1_CC5_SEL | ADC_TEST_CHL_CFG_TIM1_CC4_SEL | ADC_TEST_CHL_CFG_TIM1_TRGO_SEL)

#define   TEST_EXT_TIM1_NONE        0
#define   TEST_EXT_TIM1_TRGO        ADC_TEST_CHL_CFG_TIM1_TRGO_SEL
#define   TEST_EXT_TIM1_CC4         ADC_TEST_CHL_CFG_TIM1_CC4_SEL
#define   TEST_EXT_TIM1_CC5         ADC_TEST_CHL_CFG_TIM1_CC5_SEL
#define   TEST_EXT_TIM1_CC6         ADC_TEST_CHL_CFG_TIM1_CC6_SEL
#define   TEST_EXT_TIM2_TRGO        ADC_TEST_CHL_CFG_TIM2_TRGO_SEL
#define   TEST_EXT_TIM3_TRGO        ADC_TEST_CHL_CFG_TIM3_TRGO_SEL
#define   TEST_EXT_GPIO_TRGI        ADC_TEST_CHL_CFG_EXT_TRIG_SEL
#define   IS_TEST_EXT_TIM(TEST_EXT_TIM) (TEST_EXT_TIM <= (TEST_EXT_TIM1_TRGO | TEST_EXT_TIM1_CC4 | TEST_EXT_TIM1_CC5 | \
                                                          TEST_EXT_TIM1_CC6 | TEST_EXT_TIM2_TRGO | TEST_EXT_TIM3_TRGO | TEST_EXT_GPIO_TRGI))
/**
  * @}
  */

/** @defgroup ADC_test_ext_trig ADC_test_ext_trig
  * @{
  */
#define   TEST_EXT_TRIG_DIS                     (0<<ADC_TEST_CHL_CFG_TRIG_CFG_Pos)
#define   TEST_EXT_TRIG_RISING                  (1<<ADC_TEST_CHL_CFG_TRIG_CFG_Pos)
#define   TEST_EXT_TRIG_FALLING                 (2<<ADC_TEST_CHL_CFG_TRIG_CFG_Pos)
#define   TEST_EXT_TRIG_RISING_FALLING          (3<<ADC_TEST_CHL_CFG_TRIG_CFG_Pos)
#define   IS_TEST_EXT_TRIG(TEST_EXT_TRIG) (((TEST_EXT_TRIG) == TEST_EXT_TRIG_DIS) || ((TEST_EXT_TRIG) == TEST_EXT_TRIG_RISING) || \
                  ((TEST_EXT_TRIG) == TEST_EXT_TRIG_FALLING) || ((TEST_EXT_TRIG) == TEST_EXT_TRIG_RISING_FALLING))
/**
  * @}
  */


/** @defgroup ADC_test_ext_trig_dly ADC_test_ext_trig_dly
  * @{
  */
#define   TEST_EXT_TRIG_DLY0                        (0<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   TEST_EXT_TRIG_DLY1                        (1<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   TEST_EXT_TRIG_DLY2                        (2<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   TEST_EXT_TRIG_DLY3                        (3<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   TEST_EXT_TRIG_DLY4                        (4<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   TEST_EXT_TRIG_DLY5                        (5<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   TEST_EXT_TRIG_DLY6                        (6<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   TEST_EXT_TRIG_DLY7                        (7<<ADC_TEST_CHL_CFG_TRIG_DLY_CNT_Pos)
#define   IS_TEST_EXT_TRIG_DLY(TEST_EXT_TRIG_DLY) (((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY0) || ((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY1) || \
                  ((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY2) || ((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY3) || ((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY4) ||\
                    ((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY5) || ((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY6) || ((TEST_EXT_TRIG_DLY) == TEST_EXT_TRIG_DLY7))
/**
  * @}
  */


/** @defgroup ADC_test_que_mode ADC_test_que_mode
  * @{
  */
#define   TEST_QUE_MODE_SINGLE_SH               0
#define   TEST_QUE_MODE_BK                      1
#define   IS_TEST_QUE_MODE(TEST_QUE_MODE) (((TEST_QUE_MODE) == TEST_QUE_MODE_SINGLE_SH) || \
                                           ((TEST_QUE_MODE) == TEST_QUE_MODE_BK))
/**
  * @}
  */


/** @defgroup ADC_sample_hold ADC_sample_hold
  * @{
  */
#define   SH_SAMPLE_HOLD_1_Cycles                           ((uint32_t)0x00000000)
#define   SH_SAMPLE_HOLD_5_Cycles                           ((uint32_t)0x00000001)
#define   SH_SAMPLE_HOLD_9_Cycles                           ((uint32_t)0x00000002)
#define   SH_SAMPLE_HOLD_13_Cycles                          ((uint32_t)0x00000003)
#define   IS_SH_SAMPLE_HOLD(SH_SAMPLE_HOLD) (((SH_SAMPLE_HOLD) == SH_SAMPLE_HOLD_1_Cycles) || ((SH_SAMPLE_HOLD) == SH_SAMPLE_HOLD_5_Cycles) || \
                                             ((SH_SAMPLE_HOLD) == SH_SAMPLE_HOLD_9_Cycles) || ((SH_SAMPLE_HOLD) == SH_SAMPLE_HOLD_13_Cycles))
/**
  * @}
  */

/** @defgroup ADC_gain_fix ADC_gain_fix
  * @{
  */
#define   IS_GAIN_FIX(GAIN_FIX) ((GAIN_FIX) < 0x40 )
/**
  * @}
  */


/**
  * @}
  */

/** @defgroup ADC_Exported_Functions ADC_Exported_Functions
  * @{
  */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

void ADC_SoftDly(uint32_t time);
void ADC_StructInit(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_Queue_StructInit(ADC_TypeDef *ADCx, Queue_InitTypeDef *Queue_InitStruct);

/******************************* ADC_SYSCFGR1 *******************************/
void ADC_DeInit(ADC_TypeDef *ADCx);
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_Queue_Init(ADC_TypeDef *ADCx, Queue_InitTypeDef *Queue_InitStruct);
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void SH_Cmd(ADC_TypeDef *ADCx, uint32_t SHx, FunctionalState NewState);
void ADC_ClockDivConfig(ADC_TypeDef *ADCx, uint32_t ADC_ClockDiv);
void ADC_TrigDivConfig(ADC_TypeDef *ADCx, uint32_t ADC_TrigDiv);
void ADC_DMACmd(ADC_TypeDef *ADCx, uint32_t DMA_CHANNEL, FunctionalState NewState);
void ADC_PowerModeConfig(ADC_TypeDef *ADCx, uint32_t PowerMode);

/******************************* ADC_ISR *******************************/
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint32_t ADC_IT);
ITStatus ADC_GetITFlag(ADC_TypeDef *ADCx, uint32_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_IT);

/******************************* ADC_IER *******************************/
void ADC_ITConfig(ADC_TypeDef *ADCx, uint32_t ADC_IT, FunctionalState NewState);


/******************************* ADC_SQUEn_CFG1 *******************************/
void ADC_QueCmd(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);
void ADC_QueModeConfig(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t QueMode);
void ADC_QuePriorityConfig(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t QuePriority);
uint32_t ADC_GetCurQueState(ADC_TypeDef *ADCx, uint32_t Quex);
void ADC_QueStop(ADC_TypeDef *ADCx, uint32_t Quex);
void ADC_QueSwTrig(ADC_TypeDef *ADCx, uint32_t Quex);
void ADC_QueElementCmd(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t Element, FunctionalState NewState);

/******************************* ADC_SQUEn_CFG2 *******************************/
void ADC_QueCirCmd(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);
void ADC_ExtGpioTrigCmd(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);
void ADC_ExtTrigConfig(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t TrigSourse, uint32_t TrigEdge);
void ADC_ExtTrigDly(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t DelayCnt);
void ADC_ChannelReplaceCMD(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);
void ADC_ExtTrigFilterCMD(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);
void ADC_DiscenCMD(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);

/******************************* ADC_QUEn_AVERAGE *******************************/
uint16_t ADC_GetAverageConversionValue(ADC_TypeDef *ADCx, uint32_t Quex);
void ADC_AverageQueElementCmd(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t Element, FunctionalState NewState);
void ADC_AverageQueCmd(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);
uint16_t ADC_IsAverageRefreshInd(ADC_TypeDef *ADCx, uint32_t Quex);
void ADC_AverageOverOpt(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);

/******************************* ADC_SQUEn_ELEMENT *******************************/
void ADC_QueueElementConfig(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t NumXstChl, uint32_t Channel);

/******************************* ADC_CHLn_RESULT *******************************/
uint16_t ADC_GetChannelConversionValue(ADC_TypeDef *ADCx, uint32_t Channel);
void ADC_ChannelOverOpt(ADC_TypeDef *ADCx, uint32_t Channel, FunctionalState NewState);
uint16_t ADC_IsChannelRefreshInd(ADC_TypeDef *ADCx, uint32_t Channel);

/******************************* ADC_COMM_RESULT *******************************/
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
void ADC_CommonOverOpt(ADC_TypeDef *ADCx, FunctionalState NewState);
uint16_t ADC_IsTestInd(ADC_TypeDef *ADCx);
uint16_t ADC_IsRefreshInd(ADC_TypeDef *ADCx);
void ADC_ClrRefreshInd(ADC_TypeDef *ADCx);

/******************************* ADC_CYCLE_DLY_CFG *******************************/
void ADC_SHSamplecycle(ADC_TypeDef *ADCx,  uint32_t Value);
void ADC_AdcSamplecycle(ADC_TypeDef *ADCx,  uint32_t Quex,  uint32_t Value);
void ADC_SETResolution(ADC_TypeDef *ADCx, uint32_t ADC_Resolution);
void ADC_EOCSOCDistance(ADC_TypeDef *ADCx, uint32_t ADC_Distance);
void ADC_ChlHold(ADC_TypeDef *ADCx, uint32_t ADC_Chl_Hold);
void ADC_SH_Sample_Hold(ADC_TypeDef *ADCx, uint32_t value);

/******************************* ADC_OFFSET_CFG1 *******************************/
void ADC_SHxSignCmd(ADC_TypeDef *ADCx, uint32_t SHx, FunctionalState NewState);

/******************************* ADC_CHLn_COMP_CFG *******************************/
void ADC_CompUpCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_CompDownCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_CompDownValue(ADC_TypeDef *ADCx, uint32_t Value);
void ADC_CompUpValue(ADC_TypeDef *ADCx, uint32_t Value);

/******************************* ADC_TEST_CHL_CFG *******************************/
void ADC_TestChannelConfig(ADC_TypeDef *ADCx, uint32_t Channel);
void ADC_TestQuePriorityConfig(ADC_TypeDef *ADCx, uint32_t QuePriority);
void ADC_TestQueCirCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_TestQueSwTrig(ADC_TypeDef *ADCx);
void ADC_TestQueCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_TestFilterCMD(ADC_TypeDef *ADCx,  FunctionalState NewState);
void ADC_TestTrigSel(ADC_TypeDef *ADCx,  uint32_t Value);
void ADC_TestExtTrigConfig(ADC_TypeDef *ADCx, uint32_t Triger);
void ADC_TestExtTrigDly(ADC_TypeDef *ADCx,  uint32_t DelayCnt);
void ADC_TestQueModeConfig(ADC_TypeDef *ADCx,  uint32_t Value);

/******************************* ADC_SQUEn_REPLACE *******************************/
uint32_t ADC_ChannelReplaceConfig(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t NumXstChl, uint32_t ChannelRep);

/******************************* ADC_TEST_MODE *******************************/
void ADC_QueBkCmd(ADC_TypeDef *ADCx, uint32_t Quex, FunctionalState NewState);
void ADC_GainCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_GainConfig(ADC_TypeDef *ADCx, uint32_t GainFix);

void ADC_PhaseOffsetCtrl(ADC_TypeDef *ADCx, uint32_t Quex, uint32_t PHAchannel, uint32_t PHBchannel);
void ADC_WritePhaseOffset(ADC_TypeDef *ADCx, uint16_t PhaseAOffset, uint16_t PhaseBOffset);
uint16_t ADC_ReadPhaseBValue(ADC_TypeDef *ADCx);
uint16_t ADC_ReadPhaseAValue(ADC_TypeDef *ADCx);
#endif  /* End of __MYG0025_adc__ */

/**
  * @}
  */

/**
  * @}
  */

/***************************** (C) COPYRIGHT Metanergy  *******************************/
